Weighted summing circuit

ABSTRACT

A weighted summing circuit for minimizing bias voltage influence includes capacitive coupling and a closed loop inverter. The weighted summing circuit inputs the output of a capacitive coupling CP 1  to serially connected first and second inverters INV 1  and INV 2 , and includes grounded weighted capacitances C 32  and C 11 , capacitance C 21  connecting the first and the second inverters INV 1  and INV 2 , and a capacitive coupling CP 1  such that the closed loop gains of the first and second inverters INV 1  and INV 2  are substantially equal. The closed loop gains of the first and second inverters INV 1  and INV 2  are balanced.

FIELD OF THE INVENTION

The present invention relates to a weighted summing circuit, especiallyto a weighted summing circuit using a capacitive coupling.

BACKGROUND OF THE INVENTION

In recent years, digital computer uses have been limited because of anexponential increase in the cost of fine processing technology. As aresult, analog computers have been given attention. A weighted summingcircuit in an analog computer is formed by capacitive coupling; that is,connecting a plurality of capacitances in parallel to realize amultiplication circuit. However, such a construction leads to lowaccuracy for generated bias voltage caused by an unfitted thresholdvalue where a closed loop inverter is used to compensate the accuracy ofoutput.

SUMMARY OF THE INVENTION

The present invention solves the conventional problems by providing aweighted summing circuit for minimizing the influence of bias voltage.The weighted summing circuit is provided with capacitive coupling and aclosed loop inverter.

A weighted summing circuit according to the present invention, in acomposition wherein an output of a capacitive coupling is input toserially connected first and second inverters, connects a groundedweighted capacitance to a capacitance connecting the first and thesecond inverters and a capacitive coupling such that the closed loopgain of the first and the second inverters are substantially equal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an embodiment of a weighted summingcircuit relating to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the secondembodiment of the present invention using a weighted summing circuit.

FIG. 3 is a circuit diagram showing an embodiment of a multiplicationcircuit according to the present invention relating to a weightedsumming circuit.

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

Hereinafter, an embodiment according to the present invention isdescribed with reference to the attached drawings.

In FIG. 1, a weighted summing circuit serially connects a capacitivecoupling CP₁, and inverters INV₁ and INV₂. CP₁ includes capacitances C₀and C₁ connected in parallel.

The output of INV₁ is fed back to its input through capacitance C₁₀, andis input to INV₂ through capacitance C₂₁. The output of INV₂ is fed backto its input through capacitance C₃₁. Furthermore, weighted capacitancesC₁₁ and C₃₂ are connected in parallel to CP₁ and C₂₁, respectively.

In CP₁, voltages V₁ and V₂ are input to capacitances C₀ and C₁,respectively.

The output voltages of INV₁ and INV₂ are equal, and their value is Voff.If the input and output voltages of INV₁ are V₃ and V₄, respectively,and the input voltage of INV₂ is V₅, then formula (1) is obtained.

    (C.sub.0 V.sub.1 +C.sub.1 V.sub.2 +C.sub.10 V.sub.4)/(C.sub.0 +C.sub.1 +C.sub.10 -C.sub.11)=V.sub.3                              (1)

Formula (1) may be restated as formula (2).

    V.sub.4 ={V.sub.3 (C.sub.0 +C.sub.1 +C.sub.10 -C.sub.11)-(C.sub.0 V.sub.1 +C.sub.1 V.sub.2)}/C.sub.10                               (2)

Formula (3) may be restated as formula (4).

    (C.sub.21 V.sub.4 +C.sub.31 V.sub.out)/(C.sub.21 +C.sub.31 -C.sub.32)=V.sub.5                                        (3)

    V.sub.out ={V.sub.5 (C.sub.21 +C.sub.31 -C.sub.32)-C.sub.21 V.sub.4 }/C.sub.31                                                (4)

If formula (2) is applied to formula (4), then formula (5) is obtained.

    V.sub.out =V.sub.5 (C.sub.21 +C.sub.31 -C.sub.43)/C.sub.31 -V.sub.3 C.sub.21 (C.sub.0 +C.sub.1 +C.sub.10 -C.sub.11)/C.sub.10 C.sub.31 -(C.sub.0 V.sub.1 +C.sub.1 V.sub.2)C.sub.21 /C.sub.10 C.sub.31(5)

If V₁ =V₂ =0, then V₃ =V₅ =V_(off), and formula (6) is established.

    V.sub.out =V.sub.off (C.sub.21 +C.sub.31 -C.sub.32)/C.sub.31 -V.sub.off C.sub.21 (C.sub.0 +C.sub.1 +C.sub.10 -C.sub.11)/C.sub.10 C.sub.31(6)

If the offset is deleted, then V_(out) =0. The right side of formula (6)becomes 0.

    (C.sub.21 +C.sub.31 -C.sub.32)C.sub.10 =(C.sub.0 +C.sub.1 +C.sub.10 -C.sub.11)C.sub.21 ∴(C.sub.21 +C.sub.31 -C.sub.32)C.sub.21 =(C.sub.0 +C.sub.1 +C.sub.10 -C.sub.11)/C.sub.10          (7)

Formula (7) shows that closed loop gains of INV₁ and INV₂ are equal.

If C₁₁ and C₃₂ do not exist, then formula (8) is obtained.

    C.sub.32 /C.sub.21 =(C.sub.0 +C.sub.1)/C.sub.10            (8)

In this case, the range of C₀, C₁, C₁₀, C₂₁ and C₃₂ is very limited.That is, due to the weighted capacitances C₁₁ and C₃₂, there is anincreased degree of freedom in setting the range of C₀, C₁, C₁₀, C₂₁ andC₃₂.

FIG. 2 is a second embodiment of the present invention. It includes acapacitive coupling CP₁, an inverter INV₁, a capacitive coupling CP₂, aninverter INV₂, and a capacitive coupling CP₃. The output of CP₃ isconnected to inverter INV₃. The output of each inverter INV₁, INV₂ andINV₃ is fed back to its respective input through capacitances C₁₀, C₁₂and C₃₁, respectively. The outputs of CP₁, CP₂ and CP₃ are eachconnected to ground through weighted capacitances C₁₁, C₁₃ and C₃₂,respectively.

In CP₁ and CP₂, input voltages V₁, V₂, V₃ and V₄ are input tocapacitances C₀, C₁, C₂ and C₃. As mentioned, if the input and outputvoltages of INV₁ and INV₂ are defined as V₅, V₆, V₇ and V₈ and an inputvoltage of INV₃ is defined as V₉, then formulas (9), (10) and (11) areobtained. ##EQU1## Formulas (9) and (10) may be input to (11) to obtainformula (12). ##EQU2## Just as in the circuit of FIG. 1, when V₁ =V₂ =V₃=V₄ =0, when V₅ =V₇ =V₉ =V_(off), so formula (13) is obtained.

    V.sub.out =V.sub.off (C.sub.21 +C.sub.22 +C.sub.31 -C.sub.32)/C.sub.31 -V.sub.off (C.sub.0 +C.sub.1 +C.sub.10 -C.sub.11)C.sub.21 /C.sub.10 C.sub.31 -V.sub.off (C.sub.2 +C.sub.3 +C.sub.12 -C.sub.13)C.sub.22 /C.sub.12 C.sub.31                                        (13)

If the offset voltage is deleted, then V_(out) =0, as the right side offormula (12) becomes 0.

Formula (14) shows that the closed loop gains of INV₁ and INV₂ weightedby summing by CP₃ is equal to the closed loop gain of INV₃. Also,weighted capacitances C₁₁, C₁₃ and C₃₂ help to increase the degree offreedom of setting C₀, C₁, C₂, C₃, C₁₀, C₁₂, C₂₁, C₂₂ and C₃₁.

    (C.sub.21 +C.sub.22 +C.sub.31 -C.sub.32)/C.sub.31 =(C.sub.21 /C.sub.31)(C.sub.0 +C.sub.1 +C.sub.10 -C.sub.11)/C.sub.10 +(C.sub.22 /C.sub.31)(C.sub.2 +C.sub.3 +C.sub.12 -C.sub.13)/C.sub.12 (14)

A third embodiment of a multiplication circuit according to the presentinvention will now be described with reference to FIG. 3.

In FIG. 3, a multiplication circuit has switching means SW₀ to SW₇ toselectively input analog data V_(in), and these switching means arecontrolled by each of digital data bits b₀ to b₇, respectively.Switching means SW₀ to SW₃ are connected to a first group ofcapacitances C₀ to C₃, respectively, SW₄ to SW₇ are connected to asecond group of capacitances C₄ -C₇, respectively, and group is unitedby capacitive coupling CP₁ and CP₂.

Capacitive coupling CP₁ is composed of capacitances C₀ to C₃, and CP₂ iscomposed of capacitances C₄ to C₇, C₀ to C₃ have capacitances inproportion to the weights of b₀ to b₃. C₄ to C₇ have capacities inproportion to the weights of b₄ to b₇. Furthermore, CP₁ and CP₂ aregrounded through capacitances C₁₁ and C₁₃.

The outputs of CP₁ and CP₂ are input to inverters INV₁ and INV₂ and theoutputs of each inverter INV₁ and INV₂ are coupled by a capacitivecoupling CP₃. The output of CP₃ is output as analog data V_(out) throughinverter INV₃. CP₃ is grounded through capacitance C₃₂.

INV₁ to INV₃ are 3 serially connected inverter circuits and theconfiguration guarantees the output accuracy of each inverter. Eachinverter's output is fed back to its input through C₁₀, C₁₂ and C₃₁,respectively, and the capacitance values are set in formulas (15), (16)and (17).

    C.sub.10 -C.sub.11 =C.sub.0 +C.sub.1 +C.sub.2 +C.sub.3     (15)

    C.sub.12 -C.sub.13 =C.sub.4 +C.sub.5 +C.sub.6 +C.sub.7     (16)

    C.sub.31 -C.sub.32 =C.sub.21 +C.sub.22                     (17)

If the gain of INV₁ to INV₃ is G, the impressed voltages of C₀ to C₇ areV₀ to V₇, the input voltages of INV₁ and INV₂ are V₁₁ and V₁₂, theoutput voltages are V₂₁ and V₂₂ and the input voltage of INV₃ is V₃₁,then formulas (18) and (19) are obtained. ##EQU3## Formulas (20) to (23)lead to formula (24).

    C.sub.21 V.sub.21 +C.sub.22 V.sub.22 +C.sub.31 (V.sub.31 -V.sub.out)+C.sub.32 V.sub.31 =0                          (20)

    V.sub.21 =GV.sub.11, V.sub.22 =GV.sub.12, V.sub.out =GV.sub.31(21) ##EQU4##

    V.sub.out =(C.sub.21 V.sub.21 +C.sub.22 V.sub.22)/C.sub.31 (24)

SW_(i) is connected with V_(in) or ground depending upon the relevantcontrol bit b₀ to b₇. Thus, V_(i) =V_(in) or 0.

    C.sub.i =2.sup.i ×C.sub.u (i=0 to 3)                 (25)

    C.sub.i =2.sup.i-4 ×C.sub.u (i=4 to 7)               (26)

    C.sub.11 =C.sub.13 =C.sub.32 =C.sup.u                      (27)

C_(u) is a unit of capacitance.

    C.sub.22 =2.sup.4 ×C.sub.21                          (28)

    C.sub.31 =2.sup.4 ×C.sub.u                           (29)

If formulas (25) to (29) are defined, then the total output is amultiplication result of analog data and digital data as shown below.##EQU5## If formula (31) is defined, then formula (32) is obtained. Ithas twice the value of formula (30). By controlling level, a range ofcapacitances can be selected.

    C.sub.31 =2.sup.3 ×C.sub.u                           (31) ##EQU6## Obviously, from formula (26), it is enough for a range of capacitances from C.sub.0 to C.sub.7 to be 2.sup.3 order because the weight of bits b.sub.0 to b.sub.3 of digital data and b.sub.4 to b.sub.7 of digital data are determined as different groups and the group weights are multiplied to result in a higher group.

As mentioned above, a weighted summing circuit according to the presentinvention in a composition inputting an output of a capacitive couplingto serially connected first and second inverters and grounded weightedcapacitance is connected to a capacitance and a capacitive couplingconnecting the first and the second inverters such that the closed loopgains of the first and second inverters are substantially equal. Then,the closed loop gains of the first and the second inverters are balancedso that bias voltage influence is minimized.

What is claimed is:
 1. A weighted summing circuit comprising:acapacitive coupling having a plurality of inputs and an output, eachinput receiving one of a plurality of input voltages, said capacitivecoupling generating a weighted sum of said plurality of input voltages;a first inverter connected to said output of said capacitive coupling,said first inverter having a first inverter input and a first inverteroutput; a first feedback capacitance connected between said firstinverter input and said first inverter output; a connecting capacitancehaving a first terminal connected to said first inverter output, and asecond terminal; a second inverter having a second inverter inputconnected to said second terminal of said connecting capacitance, and asecond inverter output; a second feedback capacitor connected betweensaid second inverter output and said second inverter input; a firstgrounding capacitor connected between said first inverter input andground; and a second grounding capacitor connected between said secondinverter input and ground, wherein the closed loop gains of said firstinverter and said second inverter are substantially equal.
 2. Theweighted summing circuit of claim 1, wherein each of said plurality ofvoltages is selectively supplied to one of said inputs of saidcapacitive coupling in response to a data control signal.
 3. A weightedsumming circuit comprising:a plurality of first capacitive couplings,each having a plurality of inputs and an output, each input receivingone of a plurality of input voltages, each first capacitive couplinggenerating a weighted sum of said plurality of input voltages; aplurality of first inverters, each first inverter having a firstinverter input connected to said output of one of said plurality offirst capacitive couplings, and a first inverter output; a plurality offirst feedback capacitors, each first feedback capacitor connectedbetween said first inverter output and said first inverter input of oneof said plurality of first inverters; a plurality of first groundingcapacitors, each first grounding capacitor connected between said firstinverter input of one of said first inverters and ground; a secondcapacitive coupling having a plurality of inputs and an output, eachinput connected to one of said first inverter outputs of said pluralityof first inverters; a second inverter having a second inverter inputconnected to said output of said second capacitive coupling, and asecond inverter output; a second feedback capacitor connected betweensaid second inverter output and said second inverter input; and a secondgrounding capacitor connected between said second inverter input andground, wherein a weighted summation of the closed loop gains of saidplurality of first inverters is substantially equal to the closed loopgain of said second inverter.
 4. The weighted summing circuit of claim3, wherein each of said plurality of voltages is selectively supplied toone of said inputs of said first capacitive coupling in response to adata control signal.